The present invention relates to a semiconductor device having a trench gate structure and a method of producing the same. More specifically, the invention relates to a trench gate type semiconductor device using silicon carbide semiconductor (hereinafter abbreviated to SiC) or Group III nitride semiconductor such as AlGaN semiconductor and a method of producing the same.
When a high withstand voltage power device is produced from silicon carbide semiconductor (hereinafter referred to as SiC) or Group III nitride semiconductor (hereinafter referred to as AlGaN or the like), there is a possibility that on-state-resistance will be remarkably reduced. On-state-resistance of 5 mΩcm2 or lower is obtained by a MISFET of a 1-1.2 kV withstand voltage class using SiC. The on-state-resistance is not higher than that of an IGBT made of a silicon semiconductor (hereinafter referred to as Si) of the same withstand voltage class. There is a possibility that the majority of IGBTs made of Si as inverter parts will be replaced if cost development and performance improvement will advance in the future.
The reason why on-state-resistance can be remarkably reduced by use of SiC or AlGaN or the like is as follows. Because SiC or AlGaN or the like has a higher dielectric breakdown electric field than Si, a thinner voltage withstanding layer can be produced to obtain the same withstand voltage and resistance can be reduced by two digits or more compared with Si when the doping concentration of the voltage withstanding layer is heightened. However, use of SiC or AlGaN or the like has a bad influence on channel mobility and (gate) threshold voltage because the doping quantity or impurity concentration of a body region in a MISFET or IGBT using SiC or AlGaN or the like is high compared with Si. If the doping quantity or impurity concentration of the body region is too high, the threshold voltage becomes unnecessarily high and channel mobility is reduced remarkably, undesirably. In this respect, there is a restriction that the impurity concentration of the body region cannot be made so higher than that in the case of Si. As a result, the difference in impurity concentration between the body region and the voltage withstanding layer is small, so that the body region has characteristic that a depletion region is apt to extend.
As described above, in a MOS type semiconductor device using SiC or AlGaN or the like, the resistance of the voltage withstanding layer is reduced. As a result, the resistance of any other portion than the voltage withstanding layer, that is, channel resistance or so-called JFET resistance in a so-called DMOS type structure becomes relatively large, so that the channel resistance or JFET resistance forms a considerable resistance component. A MOS type semiconductor device having a so-called trench gate structure as a structure for eliminating the JFET resistance is known.
On the other hand, a channel length reducing method is known as a method for reducing the channel resistance. When the trench gate structure is used, it is however necessary to reduce the thickness of the body region in order to reduce the channel length. If the thickness of the body region is reduced, a punch-through state that the body region is entirely depleted is apt to be caused by the voltage applied across the device in the off-state so that the punch-through state has a bad influence on high withstand voltage characteristic inferred from the high dielectric breakdown electric field of SiC or AlGaN or the like.
Another method for reducing the channel resistance is to increase channel density per unit area. Generally, in a power device, an active region where a main current flows is formed as a set of unit cells disposed in the active region. Because a channel is always included in each unit cell, channel density per unit area can be increased when one unit cell is reduced, that is, when the cycle width (cell pitch) of the unit cells is reduced. The trench gate structure is a structure which is easy to increase channel density compared with a conventional planer gate structure.
Generally, a photolithography process is essential to production of a semiconductor device. When photolithography steps are performed in a producing process, there is required a process of mask-aligning a current-step photo pattern with a previous-step photo pattern. Generally, reduction in mask alignment accuracy becomes considerable compared with resolution as the number of mask alignment processes increases. For example, some commercially available g-line stepper produces a mask alignment error of 0.4-0.8 μm per cycle at the maximum for a resolution limit of 1 μm. The maximum of the mask alignment error varies in the aforementioned range because it is practically necessary to accept a mask alignment error up to about 0.8 μm in consideration of production efficiency though the limit of the stepper is 0.4 μm. If the number of photolithography steps is one (with no mask alignment process), the cell pitch can be reduced, for example, to 2 μm at the minimum. However, if the number of photolithography steps is two (with one mask alignment process), the cell pitch needs, for example, 3.6-5.2 μm at the minimum. Accordingly, the minimum cell pitch cannot but increase as the number of mask alignment processes increases.
On the other hand, a high-resolution (high-performance) stepper designed for Si, GaAs, etc. or a device like the stepper (hereinafter referred to as stepper or the like) has a built-in mask alignment mechanism for reducing the mask alignment error ordinarily. However, such a high-performance stepper or the like often exhibits a small focal depth because a short-wavelength light source is used. On the other hand, large and uneven warps are apt to occur in a wafer because a special bulk growth method is used for SiC or because AlGaN or the like is mainly formed on a sapphire, SiC or Si substrate by epitaxial growth. Accordingly, when the high-performance stepper or the like exhibits a small focal depth as described above, there often occurs a situation that it is impossible to perform exposure with focusing on the whole surface appropriately in one shot. As a result, a stepper having a large focal depth, that is, capable of performing mask alignment regardless of more or less warps has to be used in the meantime until the warps of the wafer will be improved with the advance of another technique in the future. Accordingly, because the aforementioned high-resolution stepper or the like cannot be used for reducing the cell pitch in SiC or AlGaN or the like, it is desired that a producing process small in the number of mask alignment processes is used for suppressing reduction of accuracy caused by accumulation of alignment errors.
When a method of doping a semiconductor such as an Si semiconductor with an impurity by a thermal diffusion method can be used as a general mass-production method, there has been already practically used a method of substantially reducing the number of mask alignment processes by self-aligning a unit cell structure, for example, as represented by an Si trench gate type MOSFET according to the related art and a method of producing the same shown in FIG. 32.
As a specific example of the cell pitch and trench width in use of the Si semiconductor which will be compared with SiC or AlGaN or the like, the trench width in use of the g-line stepper is, for example, 1 μm (equal to the resolution limit) but the cell pitch is, for example, 4 μm because of the restriction in the producing process. The restriction in the producing process will be described in detail in the following description of a Si trench gate type MOSFET and a method of producing the same.
FIG. 33 is a sectional view of important part of a semiconductor wafer. As shown in FIG. 33, a Si wafer is prepared in such a manner that n-type epitaxially grown layers 3 and 5 with a predetermined doping quantity and a predetermined thickness is formed on one principal surface (referred to as front surface) of an n-type Si semiconductor substrate 1. Hereinafter, the term “semiconductor substrate”, “Si substrate” or “SiC substrate” or especially the term “substrate” followed by the reference numeral 1 such as “substrate 1” or “SiC substrate 1” indicates a bulk substrate not input to any process yet without limitation in passing through the process, whereas the term “wafer”, “semiconductor wafer”, “Si wafer” or “SiC wafer” indicates a laminated substrate after passing through a process of depositing functional layers or regions on the bulk substrate. Then, a p-type body region 5 is formed by thermal diffusion of boron from a surface of the epitaxially grown layer into an active region portion where a main current flows. The epitaxially grown layer including the body region 5 formed in its surface further includes a portion (other than the body region 5) which remains under the body region and which is formed as a voltage withstanding layer 3. Then, an oxide film with a predetermined thickness is formed on the whole surface of the wafer and patterned appropriately to form mask oxide films 101. On this occasion, the width of each mask oxide film 101 and the distance between adjacent ones of the mask oxide films 101 can be desirably reduced to the resolution limit of the stepper used. For example, each of the width and distance is 1 μm. Incidentally, in this example, the width of each mask oxide film 101 is set at a slightly large value, for example, of 3 μm for the sake of convenience of thermal diffusion which will be performed. The sum 4 μm of the distance 1 μm and the width 3 μm of each mask oxide film is the cell pitch of unit cells which will be produced in the following description. Then, phosphorus is ion-implanted from the wafer surface with the mask oxide films 101 formed at intervals of the distance is performed and heat-treatment is performed to form source regions 6 (see FIG. 34). On this occasion, ion-implanted phosphorus is thermally diffused, so that the source regions 6 creep under the mask oxide films 101 as shown in FIG. 34. The width of each creeping portion is, for example, 1 μm. Although the allowable depth of ion implantation of phosphorus by use of a general ion implantation device is no more than about 0.8 μm, thermal diffusion permits the depth of each source region 6 (the depth of each pn junction) to increase, for example, to about 2 μm.
Then, the Si wafer is anisotropically etched from the front surface by use of the same mask oxide films 101, so that trenches 10 so deep as to reach the voltage withstanding layer 3 are formed as shown in FIG. 35 which is a sectional view of important part of the Si wafer. Then, as shown in FIG. 36 which is a sectional view of important part of the Si wafer, a gate insulating film 11 is formed on an inner wall surface of each trench 10. After a film of highly doped polycrystalline silicon (with a high doping quantity or a high impurity concentration) is then formed on the whole front surface of the wafer to protect gate pad portions (not shown), the film is etched back to embed a gate electrode 12 in the inside of each trench 10 up to a predetermined height. As a result, the gate electrode 12 in the inside of each trench 10 faces the corresponding source region 6, the corresponding body region 5 and the voltage withstanding layer 3 through the gate insulating film 11.
An appropriately doped SiO2 film is formed on the whole front surface of the wafer and etched back appropriately in the same manner as described above to thereby embed an interlayer insulating film 21 on the gate electrode 12 in the inside of each trench 10. As shown in FIG. 36, an upper end of each gate electrode 12 has to be located between lower and upper ends of the corresponding source region 6. Because each interlayer insulating film 21 is formed by a deposition method, the withstand voltage of the interlayer insulating film 21 is lower than that of a thermal oxide film. Accordingly, the interlayer insulating film 21 has to be thick in a certain degree in order to obtain a required gate withstand voltage. A production margin (dimensional margin) at etching back is also required. This production margin is given by the thickness of each source region 6 in the same manner as in each gate electrode 12. Under such circumstances, a thickness of about 2 μm as described above is therefore required as the thickness of each source region 6.
Finally, after unnecessary deposits or the like are removed from the front and rear surfaces of the wafer respectively, predetermined source electrodes 23, drain electrodes 22 and gate pad electrodes (not shown) are formed on the front and rear surfaces of the wafer respectively. Thus, the Si trench gate type MOSFET shown in FIG. 32 is completed.
Importance in the above description of the conventional Si trench gate type MOSFET and the method of producing the same with reference to FIGS. 32 to 36 lies in that the number of photolithography processes required for forming unit cell portions is only one for patterning the mask oxide films 101. In the step of etching back the polysilicon layer or the SiO2 film, a photolithography process is required for forming the gate pads or the like. However, since the unit cell portions are self-aligned without necessity of any alignment pattern, the cell pitch value can be decided regardless of pattern alignment error. As described above, since self-alignment of the unit cell portions means reduction in the number of photolithography processes required for forming the unit cell portions, it also means suppression of pattern alignment error. In this manner, since Si can be doped with an impurity by combination of an ion implantation method and a thermal diffusion method, the unit cell portions can be self-aligned so that a producing method can be provided without necessity of consideration of pattern alignment error and the cell pitch can be reduced easily.
However, in a wide band gap semiconductor such as SiC or AlGaN, the diffusion coefficient of an impurity serving as a donor or acceptor is so remarkably small that the thermal diffusion method is unrealistic. Since it is generally difficult to use the thermal diffusion method in the production line, it is impossible to self-align unit cells by the same producing method as in Si. That is, in SiC or AlGaN or the like, it is necessary to form a predetermined impurity profile not by the thermal diffusion method but by the ion implantation method for selective or local impurity doping. However, in the ion implantation method, since the impurity is little diffused in a transverse direction, one and the same mask (i.e. without pattern alignment) used in the Si wafer as shown in FIGS. 34 and 35 cannot be used for self-aligning the source regions 6 and the trenches 10. Moreover, when a general ion implantation device is used for performing ion implantation, the depth of ion implantation into each source region is 1 μm at most. For this reason, the production margin at etching back the gate electrodes 12 and the interlayer insulating films 21 is often insufficient. Accordingly, in the related art, for example, an SiC trench gate type MOSFET cannot but depend on the following unit cell structure and the method of producing the same.
FIG. 37 is a sectional view showing an important part of each unit cell portion in the SiC trench gate type MOSFET according to the related art. Since the main structure is the same as that of the Si trench gate type MOSFET shown in FIG. 32, the same constituent parts are referred to by the same reference numerals for the sake of omission of duplicate description. In FIG. 37, a characteristic point different from FIG. 32 lies in that the interlayer insulating films 21 protrude from the trenches 10. Contact holes 20 provided in the interlayer insulating films 21 are filled with a source electrode 23 so that the source electrode 23 is in ohmic contact with the front surface of the SiC wafer. In FIG. 37, highly doped body contact regions 7 of a second conductivity type are provided as regions corresponding to the surface layer of portions where the body regions 5 are exposed from the front surface of the Si wafer in FIG. 32. In FIG. 37, a region corresponding to each source region 6 in FIG. 32 is separated into a source contact region 6a of the first conductivity type and a source extension region 6b of the first conductivity type. The source contact region 6a is highly doped and formed as a surface layer of the source region 6. The source extension region 6b is formed as a lower layer of the source region 6. A surface of the body contact region 7 and a surface of the source contact region 6a are in ohmic contact with the source electrode 23 as a common electrode in the aforementioned manner.
Since FIGS. 37 and 32 are not accurate drawings in terms of dimensions, the trench width and the cell pitch in the SiC trench gate type MOSFET in FIG. 37 seem to be equal to those in FIG. 32. However, when the same g-line stepper is used for practical production, the cell pitch in SiC has to be at least 5 μm which is 25% larger than the cell pitch 4 μm in Si in FIG. 32. In consideration of production efficiency, the pitch of the trenches 10 has to be designed to be widened to 11 μm which is 175% larger than the cell pitch 4 μm in Si in FIG. 32.
The method of producing the SiC trench gate type MOSFET according to the related art shown in FIG. 37 will be described below in due order. FIG. 38 is a sectional view of important part of the SiC wafer. As shown in FIG. 38, an n-type voltage withstanding layer 3 with a predetermined doping concentration and a predetermined thickness and a p-type body layer 5 with a predetermined doping concentration and a predetermined thickness are formed successively on the whole are of one principal surface (referred to as front surface) of an n-type SiC substrate 1 by epitaxial growth.
Then, markers (not shown) for alignment in a photolithography process are formed in the same manner as the process of producing Si or the like. Then, for example, an SiO2 film is deposited and patterned to have predetermined opening portions by the same technique as Si to thereby form a mask (not shown) for performing selective ion implantation for body contact regions with a surface impurity concentration capable of obtaining ohmic contact. This step needs a photolithography process. After the wafer is then heated, for example, to 500° C., aluminum is ion-implanted to a depth of about 0.4 μm from the front surface. The depth of ion implantation is substantially decided by acceleration energy which can be achieved stably by a general 400 keV ion implantation device using monovalent aluminum. Then, heat treatment (referred to as activation annealing) is performed at a predetermined temperature for a predetermined time in an inert gas (which may contain a small amount of SiH4 or the like) to activate the ion-implanted aluminum electrically and recover implantation damage. FIG. 38 is a sectional view showing important part of the wafer in a state where activation annealing of the body contact regions 7 is completed.
Then, ion implantation and activation annealing are performed for source contact regions 6a and source extension regions 6b in the same manner as described above. For the source contact regions 6a, monovalent phosphorus ions capable of obtaining a high doping concentration sufficient to achieve ohmic contact are implanted into a depth of about 0.35 μm from the front surface. For the source extension regions 6b, for example, monovalent or divalent nitrogen ions are implanted into a depth of about 0.8 μm. Incidentally, one and the same mask can be used for the source contact regions 6a and the source extension regions 6b and activation annealing may be performed simultaneously. However, since the positional relation with the body contact regions 7 is decided by alignment in photolithography, a design has to be made appropriately to prevent the body contact regions 7 from being perfectly lost in the source contact regions 6a adjacent to the body contact regions 7 in plan view even when the maximum displacement occurs. When, for example, the aforementioned g-line stepper is used, a width of not smaller than 0.8-1.6 μm is required as the width of each body contact region 7 and it is safe that the width is not smaller than 1-2 μm in consideration of pattern conversion error. FIG. 39 is a sectional view showing important part of the wafer in a state where activation annealing of the source contact regions 6a and the source extension regions 6b is completed. Hereafter, the body layer 5 is provided as a layer under the source extension regions.
Then, as shown in FIG. 40 which is a sectional view of important part of the wafer, trenches 10 are formed in the same manner as in Si by use of an etching mask (not shown), for example, made of an SiO2 film and having appropriate opening portions. A photolithography process is required for providing appropriate opening portions in the etching mask. The width of each trench 10 may be reduced as sufficiently as possible if gate insulating films 11 and gate electrodes 12 can be formed. Each trench 10 has to be disposed in the inside of the corresponding source contact region 6a in plan view except a terminal portion of the trench 10. In addition, an end portion of each contact hole 20 which will be formed later has to be located between the trench 10 and the body contact region 7 in plan view. Accordingly, when, for example, the aforementioned g-line stepper is used, the distance between an end portion of the body contact region 7 and the end portion of the contact hole 20 and the distance between the end portion of the contact hole 20 and an end portion of the trench 10 have to be not smaller than 0.8-1.6 μm and it is safe that the distances are not smaller than 1-2 μm in consideration of pattern conversion error. From the above description, the cell pitch needs to be not smaller than 5-9 μm and it is safe that the cell pitch is not smaller than 6-11 μm in consideration of pattern conversion error. FIG. 40 is a sectional view showing important part of the wafer in a state where formation of the trenches 40 is completed. After formation of the trenches 10, the body layer 5 is separated into body regions 5 by the trenches 10. In this manner, since the method of producing the SiC device according to the related art has no self-aligning process, a large cell pitch of 6-11 μm is required compared with the cell pitch of 4 μm in the method of producing the Si device which can be produced by a self-aligning process.
After a gate insulating film 11 is then formed on an inner wall surface of each trench 10, a highly doped polysilicon layer is deposited and etched back in the same manner as in Si to thereby embed a gate electrode 12 in the trench 10 up to a predetermined height. Then, an interlayer insulating film 21 is deposited on the whole surface of the wafer. However, etching back cannot be performed differently from the case of Si because the total depth of the source contact region 6a and the source extension region 6b is no more than 0.8 μm. Instead, contact holes 20 are formed in the interlayer insulating film 21 on the front surface of the wafer so that front surfaces of the body contact regions 7 and front surfaces of the source contact regions 6a are exposed. On this occasion, photolithography is required. FIG. 41 is a sectional view showing important part of the wafer in a state where formation of the contact holes 20 is completed.
Then, for example, a nickel film and a titanium film are formed successively by sputtering so that the contact holes 20 are brought into ohmic contact with the front surfaces of the body contact regions 7 and the front surfaces of the source contact regions 6a. After the front surface of the wafer is protected by a resist or the like and unnecessary deposits or the like are removed from the rear surface of the wafer, for example, a nickel film and a titanium film are formed successively on the rear surface of the wafer by sputtering. After the resist is removed from the front surface of the wafer, heat treatment is performed to obtain ohmic contact between the drain electrode 22 and SiC and ohmic contact between the source electrode 23 and SiC. Then, an aluminum film or the like is formed appropriately and patterned in the same manner as in Si to thereby form the remaining part of the source electrode 23 and gate pad electrodes not shown. The remaining part of the drain electrode 22 is formed from a film of a predetermined metal in the same manner as in Si. Thus, the Si trench gate type MOSFET according to the related art shown in FIG. 37 is completed.
Moreover, as for a MOS semiconductor device using a wide band gap semiconductor such as SiC or AlGaN, there is pointed out a problem that the insulating film in the bottom of each trench (the bottom of each trench 10 in FIG. 37) is broken down by an excessive electric field applied to the insulating film directly because the dielectric breakdown electric field of the MOS semiconductor device is large. This is based on the fact that it is necessary to conserve not electric field intensity but electric flux density in the bottom of each trench. When the product of the relative dielectric constant and the dielectric breakdown electric field (referred to as relative dielectric constant-dielectric breakdown electric field product but a normal maximum electric field is used as the dielectric breakdown electric field when an amorphous insulator such as SiO2 is used) of the semiconductor is larger than that of the insulating film in the bottom of each trench, the insulating film is broken down earlier. For example, the relative dielectric constant-dielectric breakdown electric field product of SiO2 often used as an insulating film is about 10-12 MV/cm whereas the relative dielectric constant-dielectric breakdown electric field product of SiC reaches 15-25 MV/cm though it depends on polytype and orientation. It is conceivable that the relative dielectric constant-dielectric breakdown electric field product of AlGaN or the like is further larger. Accordingly, when a wide band gap semiconductor such as SiC or AlGaN is used, there arises a problem that breakdown of the insulating film in the bottom of each trench cannot be avoided if the structure shown in FIG. 37 is used.
As a known technique of a method of producing another SiC semiconductor device than the aforementioned SiC trench gate type MOSFET, there has been disclosed the following technique. A hard mask deposited on a p-type polycrystalline silicon layer and a shallow n-type polycrystalline silicon layer is selectively etched. While the remaining part of the hard mask is used as a mask, an n-type impurity is ion-implanted into the p-type polycrystalline silicon layer to thereby form an n-type polycrystalline silicon layer. Then, a film as a material of a side wall is deposited isotropically and etched anisotropically to thereby form a side wall on a side surface of the hard mask. While the hard mask and the side wall are used as a mask, the n-type polycrystalline silicon layer is etched. There is known a method in which the width of the n-type polycrystalline silicon layer is reduced sufficiently by self-alignment in the aforementioned manner. See, for example, JP-A-2007-27491 and corresponding EP 1915773 A1
There is a description concerned with formation of a device separation region by self-alignment in JP-A-4-209541. There is a description concerned with production of a multistage recess groove by self-alignment at a good yield rate as described in JP-A-3-184334 and JP-A-4-206838. There is a description concerned with a recess structure in which a two-stage groove structure is formed by wet etching with use of a first mask in JP-A-4-196542. There is a description concerned with a self-aligned dual-oxide UMOSFET in JP-T-2005-505138 and corresponding US Patent Appln. 2003062569 A1.
There is known a structure in which another trench than a gate trench is provided so as to be deeper than the gate trench and provided with a Schottky contact on its inner surface to protect an insulating film in the bottom of the gate trench from an excessive electric field to thereby prevent lowering of the withstand voltage as described in JP-A-8-204179 and corresponding U.S. Pat. No. 5,614,749 A.
On the other hand, a trench is formed in a wafer in which a field stopping layer, a drift layer, a current spread layer, a body region and a source contact layer are formed successively on a substrate, so that the trench reaches the field stopping layer or the substrate. A gate electrode is provided in an upper half of the trench. An insulator having a normal value of dielectric breakdown electric field equal to or larger than the dielectric breakdown electric field of the semiconductor material of the substrate is embedded in a portion of the trench deeper than the gate electrode. A semiconductor device produced in the aforementioned manner has been disclosed in JP-A-2007-194283 and corresponding US Patent Appln. 2007187695 A1
In the SiC trench gate type MOSFET, a highly doped n-type region and a highly doped p-type region can be produced by selective ion implantation but there is a problem that a long time is required for high dose ion implantation to obtain a high doping concentration. Moreover, when high dose ion implantation required for obtaining a good ohmic contact is performed particularly on the front surface of the p-type region, crystal defects are produced frequently to thereby cause a problem that the withstand voltage yield rate is lowered.
To avoid these problems, it is preferable that a highly doped p-type region can be formed by epitaxial growth but selective epitaxial growth of SiC is required for forming the region partially. However, the selective epitaxial growth of SiC is under study and has not been put to practical use sufficiently to be applied to device production. In the present situation, it is difficult to use the selective epitaxial growth of SiC. Moreover, in AlGaN or the like, it is very difficult to perform p-type high dose ion implantation itself. For example, a method of forming a quantum well by bringing alloys different in composition into contact with each other is known as another method of forming a good ohmic contact with a surface of a p-type region. It is however necessary to use this method based on epitaxial growth. Incidentally, in AlGaN or the like, it is known that selective epitaxial growth can be performed with use of an SiO2 film as a mask.
The present invention was developed in consideration of the aforementioned points, as it would be desirable to provide a trench gate type semiconductor device and a method of producing the same, in which the cell pitch can be made smaller than that in the related art even when a wide band gap semiconductor not established yet as a mass-production method for impurity doping due to a thermal diffusion method is used. It would further be desirable to provide a trench gate type semiconductor device and a method of producing the same, in which good ohmic contacts can be obtained without use of selective epitaxial growth for at least one conductivity type while the first object can be satisfied.